The present disclosure relates to semiconductor structures, and particularly to a borderless contact structure employing dual etch stop layers and methods of manufacturing the same.
As semiconductor devices shrink in each generation of semiconductor technology, formation of contact structures to gate conductors and source and drain regions of a field effect transistor become challenging because such contact structures not only need to provide reliable electrical contact to the gate conductors or the source and drain regions, but also need to avoid electrically shorting to other components. Thus, contact structures designed to provide electrical contact to a source or drain region should not contact a gate conductor, and vice versa. Since the etch chemistry employed for the anisotropic contact etch process remains the same while the lateral dimension of the dielectric gate spacer shrinks with the scaling of semiconductor devices, the likelihood of overlay variations during lithographic processes causing formation of contact structures that electrically short a source/drain region to a gate conductor of a field effect transistor increases in each generation.
The challenge of preventing undesirable electrical shorts between a contact structure and adjacent conductive structures becomes more complex when multiple exposure-and-etch schemes are employed to form contact features. Thus, there exists a need to provide a reliable and electrical-short-proof method of forming contact structures for integrated semiconductor device circuit structures.